The present embodiments relate to transistor circuits, and are more particularly directed to a memory with small aspect ratio storage cells.
The technology of many modern circuit applications continues to advance at a rapid pace, with one highly developed and incredibly prolific type of circuit being digital memory. For such memories, consideration is given to all aspects of design, including maximizing efficiency, lowering manufacturing cost, and increasing performance. These considerations may be further evaluated based on the integrated circuit device in which the memory is formed, where such circuits may be implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. One often critical factor with respect to digital memories is the cost of the device and this cost is often affected by the size of each memory cell and the overall size of the memory architecture.
In the current art, memory size may be affected by various factors. In one prior art approach as detailed later, a static random access memory (“SRAM”) memory is constructed using individual cells known as 6T cells which are constructed using a formation of six different transistors. In this as well as other SRAM cell configurations, the cell size, the overall memory size, and manufacturing cost are very much affected by the layout of the various layers or layer-formed components of the SRAM cell. For example and as detailed further later, in one prior art approach, a 6T cell is provided having an aspect ratio (i.e., bit line dimension/word line dimension) on the order of 0.50. The cell is achieved by forming each of the six transistors to have parallel gates in the word line dimension, where the n-channel active regions for each pair of access and drive transistors are formed using a continuous strip in the bit line dimension, and where the p-channel active regions for each pull-up transistor is also in the bit line dimension and isolated from the active regions of all the other transistors. However, based on the more detailed presentation of this approach provided below, one skilled in the art will appreciate that the prior art implementations of such an approach may give rise to various drawbacks.
In view of the above, and as technology advances to the next generation, there is a need to address the drawbacks of the prior art and to simplify the formation of various layers on the semiconductor substrate. The preferred embodiments described below address these drawbacks and thereby provide a more efficient and desirable integrated circuit configuration.